A Lateral Diffused Metal Oxide Semiconductor (LDMOS) transistor device is typically used to connect integrated circuits to high supply voltages beyond the internal operating voltages of the integrated circuit. The LDMOS device structure protects the gate dielectric of a transistor from dielectric breakdown due to high supply voltages by reducing the electrical field across the transistor gate oxide. The reduction of the electrical field in the “on” and “off” state is performed through a resistive element that additionally also forms an electrical field relieving structure. In the “on” state, the electrical field is released via the voltage drop across the resistive element. In the “off” state, the electrical field is reduced through the electrical field relieving structure.
In system on chip (SoC) solutions, a large amount of LDMOS devices are needed to supply different circuit parts with different supply voltages and to isolate different circuit parts, thus preventing influence on circuit performance due to supply voltage ringing through IR drops and inductive voltages generated in the supply lines during high and fast changing current supply. The LDMOS device is thus utilized for power management unit circuit parts of an integrated circuit or SoC solutions.
The area consumption of the LDMOS device is significantly determined by the flicker noise or, more generally speaking, by the low-frequency noise. The voltage noise of a LDMOS device operated in the linear region (i.e. “on” state) is given by the noise contributions from a first part, which extends from the source to the end of the transistor inversion channel and a second part, that extends from the end of the transistor inversion channel to the drain contact. The second part between the end of the transistor inversion channel and the drain contact contributes with a higher amount of noise to the total noise of the LDMOS device. So, it is desirable to reduce the noise of the second part. This increased noise contribution in the second part may originate from trapped charge associated with a trench isolation structure, which is a trench etched into the semiconductor substrate that is filled with one or more layers of dielectric material(s). The capture of a mobile charge through a trap or the emission of a trapped charge into the LDMOS current carrying mobile charge may be dependent on the distance between the trap and the mobile charge. The further the distance, the lower may be the probability for a charge capture or emission process. The influence of trapped charge in the dielectric material and/or at the semiconductor to dielectric interface on the mobile charge of the current may depend additionally on the distance between the trapped charge and the mobile charge.